Cache memories and cache controllers may be used on computer systems to improve latency of accessing frequently used data. A cache controller may be placed between a chipset (e.g., a chipset comprising a North bridge, South bridge and possibly other peripheral integrated circuits) and one or more processors (e.g., CPUs). In many computer systems, cache memories may contain a duplicate copy of a portion of a computer's main memory and may be organized in multiple levels (e.g., level one, level two, level three, and level four) according to size and/or proximity to the processor. For example, a level one (“L1”) cache memory may be closest to a processor (e.g., on the same substrate as the processor) and may implement a small amount of high performance memory that stores the most commonly requested data. If the processor cannot find the requested data in the L1 cache, the level two (“L2”) cache, which may contain a larger segment of memory, may be accessed. The process of searching the next largest cache level for the requested data may continue until the data is found. If the data is not found in one of the cache memories, the main memory may be accessed.
An increasing number of computer systems implement processors and chipsets with different communication protocols and/or physical interfaces. Cache controllers, coupled between the chipset and processor, in these mixed protocol systems may be specifically designed for one interface to communicate with a chipset using a particular protocol, and for a second interface to communicate with the processor using a different protocol. Should any one parameter change (i.e., the device with which an interface communicates or the communication protocol), another specifically designed cache controller may be required.